Clear Pin
Set Pin
Initialize
Memory
Forces the
selected
user I/O pin
low
Forces the
selected
user I/O pin
high
Initializes
DDR2
0
1
0
1
0
0x40
0x00
0x3E
0x41
0x00
0x3E
0x70
Clear Pin Command
The user I/O pin numbers are described in Table 2.
User I/O pin 0xnn is cleared. The specified user I/O
number is returned.
Set Pin Command
The user I/O pin numbers are described in Table 2.
User I/O pin 0xnn is set. The specified user I/O number
is returned.
The Initialize Memory Command configures the DDR2
SDRAM for access by the FPGA. The memory cannot
SDRAM
be accessed without being initialized .
Important Note on DDR2 SDRAM Data Access:
DDR2 SDRAM data accesses using the reference design on the DLP-HS-FPGA module are always
performed 4 bytes at a time due to the fact that the device is configured for a burst length of four.
What this means is that column address Bits 0 and 1 only change the order of the read or write bytes;
they still refer to the same 4 bytes. Therefore, to increment the DDR2 SDRAM address for
consecutive memory locations, the column address must be incremented by 4 .
Incrementing the column address by anything less than 4 simply changes the order in which the 4
bytes specified by column address 9:3 are written to the memory or returned to the user. For example,
a write to a column starting address of 0 will write to column locations 0, 1, 2 and 3. But if the user
then writes to column address 1, they will actually be writing to column locations 1, 2, 3 and 0, which
will overwrite the previous write operation.
More details on how the DDR2 SDRAM column bits 1 and 0 function can be found in Figure 4 and
Table 40 of the Micron? MT47H32M8 datasheet. For details on how the bank, row and column bits
are sent via USB to the memory, refer to the commands below:
Memory
Read
Reads 4
bytes from
0
0x8n
Reads 4 bytes from the DDR2 SDRAM starting with the
address specified. The command byte is OR’d with the
the DDR
SDRAM
Most Significant Row Address Bit (24).
n = 0 the Most Sig Row Address Bit is low (0x80)
n = 1 the Most Sig Row Address Bit is high (0x81)
1
2
3
0xah
0xam
0xal
Bits 23-16 Middle 8 bits of Row Address to be read from
Bits 15-12 Lower 4 bits of Row Address to be read from
Bits 11-8 Upper 4 bits Column Address to be read from
Bits 7-2: Lower 6 bits of Column Address to be read
from
NOTES: Refer to the text above regarding Column Bits
1 and 0 (equates to 0xal bits 3-2). Bits 1-0: Bank
Address to be read from.
If the memory has not been initialized, the data returned
will be invalid, and the command returned will be 0xE7
indicating the error.
Rev. 1.7 (May 2011)
11
? DLP Design, Inc.
相关PDF资料
DLP-IOR4 MODULE LATCHING-RELAY 4-CH
DLP-TEMP-G MODULE DATA-ACQUISITION 3-CH
DLP-TXRX-G MODULE USB-TO-TTL SRL UART CONV
DLP-USB1232H MODULE USB-TO-UART/FIFO HS 18DIP
DLP-USB232M-G MODULE USB-TO-TTL SRL UART CONV
DLP-USB232R MODULE USB-TO-SRL UART 18-DIP
DLP-USB245M-G MODULE USB-TO-TTL PARL FIFO CONV
DLP-USB245R MODULE USB-TO-PARL FIFO 18-DIP
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